288 lines
9.1 KiB
Zig
288 lines
9.1 KiB
Zig
// MARKUS MAIWALD (ARCHITECT) | VOXIS FORGE (AI)
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// Rumpk Layer 0: VirtIO-Block Driver (The Ledger)
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// - Provides persistent storage access (Sector I/O)
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const std = @import("std");
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const uart = @import("uart.zig");
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const pci = @import("virtio_pci.zig");
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extern fn malloc(size: usize) ?*anyopaque;
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var global_blk: ?VirtioBlkDriver = null;
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export fn virtio_blk_read(sector: u64, buf: [*]u8) void {
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if (global_blk) |*d| {
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d.read_sync(sector, buf);
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} else {
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uart.print("[VirtIO-Blk] Error: Driver not initialized.\n");
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}
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}
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export fn virtio_blk_write(sector: u64, buf: [*]const u8) void {
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if (global_blk) |*d| {
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d.write_sync(sector, buf);
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} else {
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uart.print("[VirtIO-Blk] Error: Driver not initialized.\n");
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}
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}
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pub fn init() void {
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if (VirtioBlkDriver.probe()) |*driver| {
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var d = driver.*;
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if (d.init_device()) {
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uart.print("[Rumpk L0] Storage initialized (The Ledger).\n");
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}
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} else {
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uart.print("[Rumpk L0] No Storage Device Found.\n");
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}
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}
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const VIRTIO_BLK_T_IN: u32 = 0;
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const VIRTIO_BLK_T_OUT: u32 = 1;
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const SECTOR_SIZE: usize = 512;
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pub const VirtioBlkDriver = struct {
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transport: pci.VirtioTransport,
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req_queue: ?*Virtqueue,
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last_used_idx: u16,
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pub fn init(transport: pci.VirtioTransport) !VirtioBlkDriver {
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var driver = VirtioBlkDriver{
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.req_queue = null,
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.transport = transport,
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.last_used_idx = 0,
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};
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if (!driver.init_device()) {
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return error.DeviceInitFailed;
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}
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return driver;
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}
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pub fn probe() ?VirtioBlkDriver {
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uart.print("[VirtIO] Probing PCI for Block device...\n");
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const PCI_ECAM_BASE: usize = 0x30000000;
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// Scan a few slots. Usually 00:02.0 if 00:01.0 is Net.
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// Or implement real PCI scan logic later.
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// For now, check slot 2 (dev=2).
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const bus: u8 = 0;
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const dev: u8 = 2; // Assuming second device
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const func: u8 = 0;
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const addr = PCI_ECAM_BASE | (@as(usize, bus) << 20) | (@as(usize, dev) << 15) | (@as(usize, func) << 12);
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const ptr: *volatile u32 = @ptrFromInt(addr);
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const id = ptr.*;
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// Device ID 0x1001 (Legacy Block) or 0x1042 (Modern Block)
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// 0x1042 = 0x1040 + 2
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if (id == 0x10011af4 or id == 0x10421af4) {
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uart.print("[VirtIO] Found VirtIO-Block device at PCI 00:02.0\n");
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return VirtioBlkDriver.init(pci.VirtioTransport.init(addr)) catch null;
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}
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// Try Slot 3 just in case
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const dev3: u8 = 3;
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const addr3 = PCI_ECAM_BASE | (@as(usize, bus) << 20) | (@as(usize, dev3) << 15) | (@as(usize, func) << 12);
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const ptr3: *volatile u32 = @ptrFromInt(addr3);
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const id3 = ptr3.*;
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if (id3 == 0x10011af4 or id3 == 0x10421af4) {
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uart.print("[VirtIO] Found VirtIO-Block device at PCI 00:03.0\n");
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return VirtioBlkDriver.init(pci.VirtioTransport.init(addr3)) catch null;
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}
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return null;
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}
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pub fn init_device(self: *VirtioBlkDriver) bool {
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// 0. Probe Transport (Legacy/Modern)
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if (!self.transport.probe()) {
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uart.print("[VirtIO-Blk] Transport Probe Failed.\n");
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return false;
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}
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// 1. Reset
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self.transport.reset();
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// 2. ACK + DRIVER
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self.transport.add_status(3);
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// 3. Queue Setup (Queue 0 is Request Queue)
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self.transport.select_queue(0);
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const q_size = self.transport.get_queue_size();
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if (q_size == 0) return false;
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self.req_queue = self.setup_queue(0, q_size) catch return false;
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// 4. Driver OK
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self.transport.add_status(4);
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global_blk = self.*;
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uart.print("[VirtIO-Blk] Device Ready. Queue Size: ");
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uart.print_hex(q_size);
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uart.print(" HeaderSize: ");
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uart.print_hex(@sizeOf(VirtioBlkReq));
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uart.print("\n");
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return true;
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}
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pub fn read_sync(self: *VirtioBlkDriver, sector: u64, buf: [*]u8) void {
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self.submit_request(VIRTIO_BLK_T_IN, sector, buf);
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}
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pub fn write_sync(self: *VirtioBlkDriver, sector: u64, buf: [*]const u8) void {
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// Cast const away because submit_request buffer logic is generic, but T_OUT implies read from buf
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self.submit_request(VIRTIO_BLK_T_OUT, sector, @constCast(buf));
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}
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// SOVEREIGN BOUNCE BUFFERS (Aligned to avoid offset bugs)
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var bounce_header: VirtioBlkReq align(16) = undefined;
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var bounce_sector: [512]u8 align(4096) = undefined;
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var bounce_status: u8 align(16) = 0;
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fn submit_request(self: *VirtioBlkDriver, type_: u32, sector: u64, buf: [*]u8) void {
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const q = self.req_queue orelse return;
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const idx = q.avail.idx % q.num;
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// Use fixed descriptors indices 0, 1, 2
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const d1 = 0;
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const d2 = 1;
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const d3 = 2;
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bounce_header.type = type_;
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bounce_header.reserved = 0;
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bounce_header.sector = sector;
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bounce_status = 0xFF;
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const VRING_DESC_F_NEXT: u16 = 1;
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const VRING_DESC_F_WRITE: u16 = 2;
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if (type_ == VIRTIO_BLK_T_OUT) {
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@memcpy(&bounce_sector, buf[0..512]);
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}
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q.desc[d1].addr = @intFromPtr(&bounce_header);
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q.desc[d1].len = @sizeOf(VirtioBlkReq);
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q.desc[d1].flags = VRING_DESC_F_NEXT;
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q.desc[d1].next = d2;
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q.desc[d2].addr = @intFromPtr(&bounce_sector);
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q.desc[d2].len = 512;
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if (type_ == VIRTIO_BLK_T_IN) {
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q.desc[d2].flags = VRING_DESC_F_NEXT | VRING_DESC_F_WRITE;
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} else {
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q.desc[d2].flags = VRING_DESC_F_NEXT;
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}
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q.desc[d2].next = d3;
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q.desc[d3].addr = @intFromPtr(&bounce_status);
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q.desc[d3].len = 1;
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q.desc[d3].flags = VRING_DESC_F_WRITE;
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q.desc[d3].next = 0;
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asm volatile ("fence" ::: .{ .memory = true });
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const avail_ring = get_avail_ring(q.avail);
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avail_ring[idx] = d1;
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asm volatile ("fence" ::: .{ .memory = true });
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q.avail.idx +%= 1;
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asm volatile ("fence" ::: .{ .memory = true });
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self.transport.notify(0);
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// Polling Used Ring
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var timeout: usize = 10000000;
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const used_ptr = q.used; // *VirtqUsed
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while (used_ptr.idx == self.last_used_idx and timeout > 0) : (timeout -= 1) {
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asm volatile ("fence" ::: .{ .memory = true });
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}
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if (timeout == 0) {
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uart.print("[VirtIO-Blk] Timeout Waiting for Used Ring!\n");
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} else {
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// Request Done.
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self.last_used_idx +%= 1; // Consume
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asm volatile ("fence" ::: .{ .memory = true });
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if (bounce_status != 0) {
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uart.print("[VirtIO-Blk] I/O Error Status: ");
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uart.print_hex(bounce_status);
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uart.print("\n");
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} else {
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if (type_ == VIRTIO_BLK_T_IN) {
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const dest_slice = buf[0..512];
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@memcpy(dest_slice, &bounce_sector);
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}
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}
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}
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}
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fn setup_queue(self: *VirtioBlkDriver, index: u16, count: u16) !*Virtqueue {
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// ...(Similar to Net)...
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// Allocate Memory
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const desc_size = 16 * @as(usize, count);
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const avail_size = 6 + 2 * @as(usize, count);
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const used_offset = (desc_size + avail_size + 4095) & ~@as(usize, 4095);
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const used_size = 6 + 8 * @as(usize, count);
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const total_size = used_offset + used_size;
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const raw_ptr = malloc(total_size + 4096) orelse return error.OutOfMemory;
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const aligned_addr = (@intFromPtr(raw_ptr) + 4095) & ~@as(usize, 4095);
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const q_ptr_raw = malloc(@sizeOf(Virtqueue)) orelse return error.OutOfMemory;
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const q_ptr: *Virtqueue = @ptrCast(@alignCast(q_ptr_raw));
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q_ptr.num = count;
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q_ptr.desc = @ptrFromInt(aligned_addr);
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q_ptr.avail = @ptrFromInt(aligned_addr + desc_size);
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q_ptr.used = @ptrFromInt(aligned_addr + used_offset);
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// Notify Device
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const phys_addr = aligned_addr;
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self.transport.select_queue(index);
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if (self.transport.is_modern) {
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self.transport.setup_modern_queue(phys_addr, phys_addr + desc_size, phys_addr + used_offset);
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} else {
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const pfn = @as(u32, @intCast(phys_addr >> 12));
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self.transport.setup_legacy_queue(pfn);
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}
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return q_ptr;
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}
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// structs ...
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const VirtioBlkReq = packed struct {
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type: u32,
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reserved: u32,
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sector: u64,
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};
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const Virtqueue = struct {
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desc: [*]volatile VirtioDesc,
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avail: *volatile VirtioAvail,
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used: *volatile VirtioUsed,
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num: u16,
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};
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const VirtioDesc = struct {
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addr: u64,
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len: u32,
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flags: u16,
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next: u16,
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};
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const VirtioAvail = extern struct {
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flags: u16,
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idx: u16,
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};
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const VirtioUsed = extern struct {
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flags: u16,
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idx: u16,
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};
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inline fn get_avail_ring(avail: *volatile VirtioAvail) [*]volatile u16 {
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return @ptrFromInt(@intFromPtr(avail) + 4);
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}
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};
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