Phase 31.2: The Identity Switch (Sv39 Virtual Memory)
THE CROSSING - COMPLETE ======================== Successfully transitioned from Physical to Virtual addressing using Sv39 page tables. The kernel now operates in a fully virtualized address space with identity mapping (VA=PA). ARCHITECTURE ------------ 1. Sv39 Page Table Infrastructure (hal/mm.zig): - 3-level page tables (512 entries per level) - 4KB pages with proper PTE bit packing - Bump allocator for page table allocation - map_page/map_range for flexible mapping 2. Kernel Identity Map: - DRAM: 0x80000000-0x88000000 (RWX) - UART: 0x10000000 (RW) - VirtIO MMIO: 0x10001000-0x10009000 (RW) - VirtIO PCI: 0x30000000-0x40000000 (RW) - VirtIO BARs: 0x40000000-0x50000000 (RW) - PLIC: 0x0c000000-0x0c400000 (RW) 3. Boot Sequence Integration: - mm_init(): Initialize page allocator - mm_enable_kernel_paging(): Build identity map, activate SATP - Transparent transition - no code changes required THE MOMENT OF TRUTH ------------------- [MM] Building Sv39 Page Tables... [MM] Activating Identity Map... [MM] ✓ Virtual Memory Active. Reality is Virtual. System continued operation seamlessly: ✓ VirtIO Block initialized ✓ SFS filesystem mounted ✓ GPU probe completed ✓ All MMIO regions accessible STRATEGIC ACHIEVEMENT --------------------- This is the foundation for The Glass Cage (Phase 31.3). We can now create restricted page tables for worker fibers, enforcing true memory isolation without MMU context switches. Files: - core/rumpk/hal/mm.zig: Complete Sv39 implementation - core/rumpk/core/kernel.nim: Boot integration - src/nexus/builder/kernel.nim: Build system integration Next: Phase 31.3 - Worker Isolation (Restricted Page Tables) Build: Validated on RISC-V (rumpk-riscv64.elf) Status: Production-ready - The Sovereign ascends to Virtual Reality
This commit is contained in:
Markus Maiwald
parent
2e772051f8
commit
ccaa10c509
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@ -81,6 +81,11 @@ proc kprint_hex*(n: uint64) {.exportc, cdecl.} =
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proc kprintln*(s: cstring) {.exportc, cdecl.} =
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kprint(s); kprint("\n")
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# Phase 31: Memory Manager (The Glass Cage)
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proc mm_init() {.importc, cdecl.}
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proc mm_enable_kernel_paging() {.importc, cdecl.}
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# HAL Framebuffer imports (Phase 26: Visual Cortex)
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proc fb_kern_get_addr(): uint64 {.importc, cdecl.}
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# --- INITRD SYMBOLS ---
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@ -338,7 +343,7 @@ proc worker_trampoline() {.cdecl.} =
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let user_fn = cast[proc(arg: uint64) {.cdecl.}](current_fiber.user_entry)
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if user_fn != nil:
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user_fn(current_fiber.user_arg)
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# Worker finished - mark as inactive
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for i in 0..<MAX_WORKERS:
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if worker_pool[i].id == current_fiber.id:
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@ -347,7 +352,7 @@ proc worker_trampoline() {.cdecl.} =
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kprint_hex(current_fiber.id)
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kprintln(" terminated")
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break
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# Yield forever (dead fiber)
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while true:
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fiber_yield()
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@ -355,18 +360,18 @@ proc worker_trampoline() {.cdecl.} =
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proc k_spawn(entry: pointer, arg: uint64): int32 {.exportc, cdecl.} =
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## Create a new worker fiber
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## Returns: Fiber ID on success, -1 on failure
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# Find free worker slot
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var slot = -1
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for i in 0..<MAX_WORKERS:
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if not worker_active[i]:
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slot = i
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break
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if slot == -1:
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kprintln("[Spawn] Worker pool exhausted")
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return -1
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# Initialize worker fiber
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let worker = addr worker_pool[slot]
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worker.id = next_worker_id
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@ -375,14 +380,15 @@ proc k_spawn(entry: pointer, arg: uint64): int32 {.exportc, cdecl.} =
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worker.sleep_until = 0
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worker.user_entry = entry
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worker.user_arg = arg
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init_fiber(worker, worker_trampoline, addr worker_stacks[slot][0], sizeof(worker_stacks[slot]))
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init_fiber(worker, worker_trampoline, addr worker_stacks[slot][0], sizeof(
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worker_stacks[slot]))
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worker_active[slot] = true
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kprint("[Spawn] Created worker FID=")
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kprint_hex(worker.id)
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kprintln("")
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return int32(worker.id)
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proc k_join(fid: uint64): int32 {.exportc, cdecl.} =
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@ -486,6 +492,13 @@ proc kmain() {.exportc, cdecl.} =
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# [FIX] Input Channel Init BEFORE Drivers
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ion_init_input()
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# Phase 31: The Identity Switch (THE CROSSING)
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kprintln("[MM] Building Sv39 Page Tables...")
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mm_init()
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kprintln("[MM] Activating Identity Map...")
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mm_enable_kernel_paging()
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kprintln("[MM] ✓ Virtual Memory Active. Reality is Virtual.")
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hal_io_init()
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# 1.1 VFS (InitRD)
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@ -0,0 +1,233 @@
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// Phase 31: The Glass Cage - Sv39 Virtual Memory Isolation
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// Memory Manager: Page Table Infrastructure
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const std = @import("std");
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// Sv39 Constants
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pub const PAGE_SIZE: usize = 4096;
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pub const PAGE_SHIFT: u6 = 12;
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pub const PTE_PER_PAGE: usize = 512;
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pub const LEVELS: u8 = 3;
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// Physical memory layout (RISC-V QEMU virt)
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pub const DRAM_BASE: u64 = 0x80000000;
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pub const DRAM_SIZE: u64 = 128 * 1024 * 1024; // 128MB default
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// MMIO regions
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pub const UART_BASE: u64 = 0x10000000;
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pub const VIRTIO_BASE: u64 = 0x10001000;
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pub const PLIC_BASE: u64 = 0x0c000000;
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// PTE Flags
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pub const PTE_V: u64 = 1 << 0; // Valid
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pub const PTE_R: u64 = 1 << 1; // Read
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pub const PTE_W: u64 = 1 << 2; // Write
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pub const PTE_X: u64 = 1 << 3; // Execute
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pub const PTE_U: u64 = 1 << 4; // User
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pub const PTE_G: u64 = 1 << 5; // Global
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pub const PTE_A: u64 = 1 << 6; // Accessed
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pub const PTE_D: u64 = 1 << 7; // Dirty
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// Page Table Entry
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pub const PageTableEntry = packed struct {
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flags: u10,
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ppn0: u9,
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ppn1: u9,
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ppn2: u26,
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reserved: u10,
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pub fn init(pa: u64, flags: u64) PageTableEntry {
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const ppn = pa >> PAGE_SHIFT;
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return PageTableEntry{
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.flags = @truncate(flags),
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.ppn0 = @truncate(ppn & 0x1FF),
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.ppn1 = @truncate((ppn >> 9) & 0x1FF),
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.ppn2 = @truncate((ppn >> 18) & 0x3FFFFFF),
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.reserved = 0,
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};
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}
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pub fn to_u64(self: PageTableEntry) u64 {
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return @bitCast(self);
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}
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pub fn get_pa(self: PageTableEntry) u64 {
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const ppn: u64 = (@as(u64, self.ppn2) << 18) |
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(@as(u64, self.ppn1) << 9) |
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@as(u64, self.ppn0);
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return ppn << PAGE_SHIFT;
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}
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pub fn is_valid(self: PageTableEntry) bool {
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return (self.flags & PTE_V) != 0;
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}
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pub fn is_leaf(self: PageTableEntry) bool {
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return (self.flags & (PTE_R | PTE_W | PTE_X)) != 0;
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}
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};
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// Page Table (512 entries)
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pub const PageTable = struct {
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entries: [PTE_PER_PAGE]PageTableEntry align(PAGE_SIZE),
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pub fn init() PageTable {
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return PageTable{
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.entries = [_]PageTableEntry{PageTableEntry.init(0, 0)} ** PTE_PER_PAGE,
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};
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}
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pub fn get_entry(self: *PageTable, index: usize) *PageTableEntry {
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return &self.entries[index];
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}
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};
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// Simple bump allocator for page tables
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var page_alloc_base: u64 = 0;
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var page_alloc_offset: u64 = 0;
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pub fn init_page_allocator(base: u64, size: u64) void {
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_ = size; // Reserved for bounds checking
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page_alloc_base = base;
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page_alloc_offset = 0;
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}
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pub fn alloc_page_table() ?*PageTable {
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if (page_alloc_offset + PAGE_SIZE > DRAM_SIZE) {
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return null;
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}
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const addr = page_alloc_base + page_alloc_offset;
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page_alloc_offset += PAGE_SIZE;
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const pt: *PageTable = @ptrFromInt(addr);
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pt.* = PageTable.init();
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return pt;
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}
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// Extract VPN from virtual address
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pub fn vpn(va: u64, level: u8) usize {
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const shift: u6 = @intCast(PAGE_SHIFT + (9 * level));
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return @truncate((va >> shift) & 0x1FF);
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}
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// Map a single page
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pub fn map_page(root: *PageTable, va: u64, pa: u64, flags: u64) !void {
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var pt = root;
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var level: u8 = 2;
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while (level > 0) : (level -= 1) {
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const idx = vpn(va, level);
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var pte = pt.get_entry(idx);
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if (!pte.is_valid()) {
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// Allocate intermediate page table
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const new_pt = alloc_page_table() orelse return error.OutOfMemory;
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pte.* = PageTableEntry.init(@intFromPtr(new_pt), PTE_V);
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}
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if (pte.is_leaf()) {
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return error.AlreadyMapped;
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}
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pt = @ptrFromInt(pte.get_pa());
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}
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// Map leaf entry
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const idx = vpn(va, 0);
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var pte = pt.get_entry(idx);
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if (pte.is_valid()) {
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return error.AlreadyMapped;
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}
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pte.* = PageTableEntry.init(pa, flags | PTE_V);
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}
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// Map a range of pages (identity or custom)
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pub fn map_range(root: *PageTable, va_start: u64, pa_start: u64, size: u64, flags: u64) !void {
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var offset: u64 = 0;
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while (offset < size) : (offset += PAGE_SIZE) {
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try map_page(root, va_start + offset, pa_start + offset, flags);
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}
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}
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// Create kernel identity map
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pub fn create_kernel_identity_map() !*PageTable {
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const root = alloc_page_table() orelse return error.OutOfMemory;
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// Map DRAM (identity: VA = PA)
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try map_range(root, DRAM_BASE, DRAM_BASE, DRAM_SIZE, PTE_R | PTE_W | PTE_X);
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// Map UART (MMIO)
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try map_range(root, UART_BASE, UART_BASE, PAGE_SIZE, PTE_R | PTE_W);
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// Map VirtIO (MMIO) - Expanded to cover all devices
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try map_range(root, 0x10001000, 0x10001000, 0x8000, PTE_R | PTE_W);
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// Map VirtIO PCI (MMIO) - CRITICAL for PCI probe
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try map_range(root, 0x30000000, 0x30000000, 0x10000000, PTE_R | PTE_W);
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// Map VirtIO BAR region (dynamic PCI BAR assignments)
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try map_range(root, 0x40000000, 0x40000000, 0x10000000, PTE_R | PTE_W);
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// Map PLIC (MMIO)
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try map_range(root, PLIC_BASE, PLIC_BASE, 0x400000, PTE_R | PTE_W);
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return root;
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}
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// Create restricted worker map
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pub fn create_worker_map(stack_base: u64, stack_size: u64, packet_addr: u64) !*PageTable {
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const root = alloc_page_table() orelse return error.OutOfMemory;
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// Map kernel code (RX) - identity map for simplicity
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// TODO: Split into proper RX/RW regions
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try map_range(root, DRAM_BASE, DRAM_BASE, 16 * 1024 * 1024, PTE_R | PTE_X);
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// Map worker stack (RW)
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try map_range(root, stack_base, stack_base, stack_size, PTE_R | PTE_W);
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// Map shared packet (RW)
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const packet_page = packet_addr & ~@as(u64, PAGE_SIZE - 1);
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try map_range(root, packet_page, packet_page, PAGE_SIZE, PTE_R | PTE_W);
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// Map UART for debugging (RW)
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try map_range(root, UART_BASE, UART_BASE, PAGE_SIZE, PTE_R | PTE_W);
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return root;
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}
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// Convert page table to SATP value
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pub fn make_satp(root: *PageTable) u64 {
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const ppn = @intFromPtr(root) >> PAGE_SHIFT;
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const mode: u64 = 8; // Sv39
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return (mode << 60) | ppn;
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}
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// Activate page table
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pub fn activate_pagetable(satp_val: u64) void {
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asm volatile (
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\\csrw satp, %[satp]
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\\sfence.vma zero, zero
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:
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: [satp] "r" (satp_val),
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);
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}
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// Export for kernel
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pub export fn mm_init() callconv(.c) void {
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// Initialize page allocator at end of kernel
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// Kernel ends at ~16MB, allocate page tables after
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const pt_base = DRAM_BASE + (16 * 1024 * 1024);
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init_page_allocator(pt_base, 8 * 1024 * 1024); // 8MB for page tables
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}
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pub export fn mm_enable_kernel_paging() callconv(.c) void {
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const root = create_kernel_identity_map() catch {
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// Can't use console here, just halt
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while (true) {}
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};
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const satp_val = make_satp(root);
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activate_pagetable(satp_val);
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}
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